The present invention generally relates to the field of communication. More specifically, an embodiment of the present invention provides a high-resolution single-ended source-synchronous receiver.
Chip-to-chip wireline communication consists of a chip sending and receiving data from another chip over wires incorporated on a board on which the communicating chips are placed. The sending chip drives the data onto the wire, otherwise known as a board trace, using a driver circuit. The receiving chip receives the data at the other end of the communication bus using a receiver circuit. The unit of data transferred may be called a bit. A chip may use a single wire to send data, wherein the communication method is called single-ended signaling, or it may use a pair of wires to send data, wherein the communication method is called differential signaling.
In Single-ended signaling, a bit is driven onto a board trace at a particular voltage level. In binary communication, where data is coded as a series of 1""s and 0""s, a 1 could be any voltage above a particular value, while a 0 could be any voltage below a certain value. The driver, therefore, when driving a 1, places a voltage step on the board trace. The performance of the complete communication system is a factor of the edge-rate and the voltage level that the driver drives onto the board trace. Generally, a faster edge-rate and a higher voltage level result in a higher performance system. In single-ended signaling, the receiving chip compares the voltage of the bit sent down the board trace against an internally generated reference voltage to resolve the identity of the bit. For example, in binary communication, the receiver resolves a bit to be a 1 if the voltage it receives is above the reference voltage, and a 0 if the voltage is below the reference voltage. A voltage step may be referred to as being composed of a set of sine waves having different frequencies. The edge rate of the voltage step can be a function of the set of frequencies, e.g., with higher frequencies resulting in a faster edge-rate.
High-speed single-ended signaling over relatively long board traces suffers from a number of important problems. The voltage step launched by the driver suffers ISI (Inter-symbol interference), skin effect, and dielectric losses on the board, especially at higher frequencies. Board losses in long traces do not only introduce attenuation of the signals, but, far more significantly, cause distortion. Distortion will in turn introduce ISI, which seriously limits the data rate. This results in a reduced data window both in voltage and time at the receiver, which makes it difficult to sample data at the receiver end.
These problems result in less separation between the data voltage and the reference voltage signals and, hence, a reduced noise margin. The noise performance of a system is generally determined based on how accurately a reference voltage is produced. As a result, an inaccurate voltage reference diminishes the performance of the signaling interface.
The present invention includes novel methods and apparatus to efficiently provide high-resolution single-ended source-synchronous receivers. In an embodiment of the present invention, a method of receiving a data signal in a source-synchronous receiver is disclosed. The method includes: providing a receiver to receive the data signal, the receiver receiving the data signal, a clock signal, and a complementary clock signal; differentially amplifying the data, clock, and complementary clock signals to provide a first output signal and a second output signal; and determining which one of the first and second output signals is provided through a combination of a high impedance signal and a logic signal.
In another embodiment of the present invention, the method includes selecting one of the first and second output signals as a receiver output signal based on the determining act.
In a further embodiment of the present invention, a source-synchronous receiver to receive a data signal is disclosed. The receiver includes: a first amplifier to receive a clock signal and the data signal, the first amplifier providing a first output signal; a second amplifier to receive a complementary clock signal and the data signal, the second amplifier providing a second output signal; a third amplifier to receive the clock signal and the data signal, the third amplifier providing a third output signal, the second and third output signals being combined to provide a fifth output; and a fourth amplifier to receive the complementary clock signal and the data signal, the fourth amplifier providing a fourth output signal, the first and fourth output signals being combined to provide a sixth output signal.
In yet another embodiment of the present invention, the receiver selects one of the fifth and sixth output signals to provide a viable receiver output signal.